Topic -3 : Bus, bus architecture and bus arbitration (COA)

 

Bus, bus architecture, and bus arbitration

A bus in computer architecture and organization refers to a communication system that transfers data between components inside a computer, such as the CPU, memory, and input/output devices. It acts like a shared highway, consisting of a set of parallel wires or conductive paths, allowing multiple components to send and receive data efficiently.

Types of Buses

There are three main types of buses used in computer architecture:

1. Data Bus: Transfers actual data (e.g., instructions or operands) between the CPU, memory, and peripherals. Its width (number of wires) determines the amount of data that can be transferred at once (e.g., 32-bit or 64-bit).
2. Address Bus: Carries memory addresses from the CPU to memory or other devices, indicating where data should be read from or written to. The width of the address bus determines the maximum memory size (e.g., a 32-bit address bus can address 4 GB).
3. Control Bus: Transmits control signals (e.g., read/write commands) from the CPU to other components to coordinate operations and manage data flow.

These buses work together to ensure smooth communication within the computer system.

Bus Architecture in computer organization refers to the structure and design of the bus system that facilitates communication between various components of a computer, such as the CPU, memory, and input/output (I/O) devices. The bus acts as a shared communication pathway, consisting of multiple wires or conductive paths grouped into sets called buses. These buses are categorized based on their function and work together to ensure efficient data transfer and system coordination.

Components of Bus Architecture

1. Data Bus: Transfers the actual data (e.g., instructions, operands) between the CPU, memory, and I/O devices. The width of the data bus (e.g., 8-bit, 16-bit, 32-bit, 64-bit) determines the amount of data that can be transferred simultaneously.
2. Address Bus: Carries the memory addresses from the CPU to specify the location of data or instructions in memory or I/O devices. The width of the address bus determines the maximum addressable memory (e.g., a 32-bit address bus supports up to 4 GB).
3. Control Bus: Transmits control signals (e.g., read, write, interrupt) from the CPU to manage and synchronize the operations of other components.

Types of Bus Architecture

1. Single Bus Architecture:
   • Description: All components (CPU, memory, I/O) are connected to a single shared bus.
   • Advantages: Simple design, cost-effective, easy to implement.
   • Disadvantages: Bottleneck due to limited bandwidth, as all data transfers compete for the same bus.
   • Example: Early personal computers with a single system bus.
2. Multiple Bus Architecture:
   • Description: Uses multiple buses to connect different components, reducing congestion. Common configurations include:
     • Two-Bus Architecture: One bus for memory and another for I/O.
     • Three-Bus Architecture: Separate buses for data, address, and control.
   • Advantages: Improved performance and parallelism, as multiple transfers can occur simultaneously.
   • Disadvantages: More complex and expensive due to additional hardware.
   • Example: Modern processors with dedicated memory and I/O buses.

Key Features of Bus Architecture

• Bus Width: The number of bits transferred at once (e.g., 32-bit or 64-bit buses).
• Bus Speed: Measured in MHz or GHz, determining the rate of data transfer.
• Bus Arbitration: Mechanism to resolve conflicts when multiple devices attempt to use the bus simultaneously (e.g., priority-based or time-sharing).
• Bus Mastering: Allows devices other than the CPU to control the bus, enhancing efficiency.

Hierarchical Bus Architecture

In modern systems, bus architecture is often hierarchical to optimize performance:

• System Bus: Connects the CPU, memory, and main system components.
• Expansion Bus: Links peripheral devices (e.g., PCI, USB) to the system bus via a bridge or controller.
• Front-Side Bus (FSB): Connects the CPU to the northbridge (memory controller).
• Back-Side Bus: Connects the CPU to the cache memory (in some designs).

Advantages

• Simplifies communication between components.
• Supports modularity and scalability.
• Enables easy upgrades via expansion buses.

Disadvantages

• Can become a performance bottleneck in single-bus systems.
• Complex arbitration in multi-bus systems.
• Limited by physical constraints like bus length and capacitance.

Example

In a typical PC, the CPU communicates with RAM via the front-side bus, while peripherals like graphics cards use the PCI Express bus, all coordinated through a chipset.

Bus Arbitration is a mechanism in computer architecture that determines which device or component gains control of the bus when multiple devices request access simultaneously. Since the bus is a shared resource, arbitration prevents conflicts and ensures orderly data transfer between the CPU, memory, and I/O devices.

How Bus Arbitration Works

When multiple devices (e.g., CPU, DMA controllers, or peripherals) need to use the bus, they send a request signal. The arbitration process resolves these requests based on predefined rules or protocols. Once a device is granted access, it can transmit data until its task is complete, after which the bus is released for the next requester.

Types of Bus Arbitration

1. Centralized Arbitration:

• A central controller (e.g., a bus arbiter in the CPU or chipset) evaluates requests and grants access.
• Advantages: Simple to implement, centralized control.
• Disadvantages: Single point of failure, potential bottleneck.
• Example: Daisy-chaining, where devices are prioritized based on their position in a chain.

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1. Distributed Arbitration:
   • All devices participate in deciding who gets bus access, often using a self-arbitration protocol.
   • Advantages: No single point of failure, more scalable.
   • Disadvantages: Complex implementation.
   • Example: Token-passing or collision-detection methods like in Ethernet.

Common Arbitration Techniques

• Priority-Based Arbitration: Devices are assigned priorities (e.g., CPU has the highest priority). The highest-priority request is granted first.
• Time-Slicing (Round-Robin): Each device gets equal time slots to use the bus in a cyclic order.
• Daisy-Chaining: Devices are connected in a chain, and a control signal passes from one to the next, granting access to the first available device.
• Polling: The controller checks each device sequentially to see if it needs the bus.

Key Features

• Fairness: Ensures all devices get a chance to use the bus over time.
• Efficiency: Minimizes wait times and maximizes bus utilization.
• Latency: Time taken to resolve arbitration affects system performance.

Importance

• Prevents data corruption or crashes due to simultaneous bus access.
• Critical in systems with multiple masters (e.g., multi-core CPUs, DMA controllers).